1. Field of the Invention
This invention relates to a semiconductor device comprising a capacity element.
2. Description of the Related Art
A conventional semiconductor device comprising a capacity element has been disclosed in, for example, Japanese Laid-open patent publication No. 2001-237375. The application has described an MIM (Metal Insulator Metal) capacitor. There has been also described that an MIM capacitor comprising a Cu electrode is formed by a damascene process, due to which dishing is caused in the Cu electrode.
After intense investigation, the present inventors have found that dishing described in Japanese Laid-open patent publication No. 2001-237375 significantly affects an element forming process particularly when being generated in a lower electrode among electrodes in the MIM capacitor. Dishing in the lower electrode may cause variation in a thickness in a capacitor film formed on the lower electrode, and furthermore, variation in a structure of the lower electrode itself or of an upper electrode formed on the capacitor film.
Therefore, it would be effective to prevent dishing in a lower electrode by the most convenient method for reliably forming a capacity element.